JPH0432579U - - Google Patents
Info
- Publication number
- JPH0432579U JPH0432579U JP7393090U JP7393090U JPH0432579U JP H0432579 U JPH0432579 U JP H0432579U JP 7393090 U JP7393090 U JP 7393090U JP 7393090 U JP7393090 U JP 7393090U JP H0432579 U JPH0432579 U JP H0432579U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- wires
- routing guide
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Insertion, Bundling And Securing Of Wires For Electric Apparatuses (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7393090U JPH0432579U (en]) | 1990-07-13 | 1990-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7393090U JPH0432579U (en]) | 1990-07-13 | 1990-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0432579U true JPH0432579U (en]) | 1992-03-17 |
Family
ID=31613176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7393090U Pending JPH0432579U (en]) | 1990-07-13 | 1990-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0432579U (en]) |
-
1990
- 1990-07-13 JP JP7393090U patent/JPH0432579U/ja active Pending